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| CY7C0430BV CY7C0430CV 10 Gb/s 3.3V QuadPortTM DSE Family Features * QuadPortTM datapath switching element (DSE) family allows four independent ports of access for data path management and switching * High-bandwidth data throughput up to 10 Gb/s * 133-MHz[1] port speed x 18-bit-wide interface x 4 ports * High-speed clock to data access 4.2 ns (max.) * Synchronous pipelined device -- 1-Mb (64K x 18) switch array * 0.25-micron CMOS for optimum speed/power * IEEE 1149.1 JTAG boundary scan * Width and depth expansion capabilities * BIST (Built-In Self-Test) controller * Dual Chip Enables on all ports for easy depth expansion * Separate upper-byte and lower-byte controls on all ports * Simple array partitioning -- Internal mask register controls counter wrap-around -- Counter-Interrupt flags to indicate wrap-around -- Counter and mask registers readback on address * 272-ball BGA package (27-mm x 27-mm x 1.27-mm ball pitch) * Commercial and industrial temperature ranges * 3.3V low operating power -- Active = 750 mA (maximum) -- Standby = 15 mA (maximum QuadPort DSE Family Applications PORT 1 PORT 3 PORT 2 PORT 4 BUFFERED SWITCH PORT 2 PORT 1 PORT 3 PORT 4 REDUNDANT DATA MIRROR Note: 1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz. Cypress Semiconductor Corporation Document #: 38-06027 Rev. *B * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 23, 2006 CY7C0430BV CY7C0430CV PORT 1 PORT 2 PORT 4 PORT 3 DATA PATH AGGREGATOR Processor 1 Pre-processed DATA Path QuadPort DSE Family Processed DATA Path Processor 2 DATA PATH MANAGER FOR PARALLEL PACKET PROCESSING Queue #1 PORT 1 PORT 3 Queue #2 PORT 2 PORT 4 DATA CLASSIFICATION ENGINE Functional Description The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another. Each port can read or write up to 133 MHz[1], giving the device up to 10 Gb/s of data throughput. The device is 1-Mb (64K x 18) in density. Simultaneous reads are allowed for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed. Any port can write to a certain location while other ports are reading that location simultaneously, if the timing spec for port to port delay (tCCS) is met. The result of writing to the same location by more than one port at the same time is undefined. Data is registered for decreased cycle time. Clock to data valid tCD2 = 4.2 ns. Each port contains a burst counter on the input Document #: 38-06027 Rev. *B address register. After externally loading the counter with the initial address the counter will self-increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle is required with chip enables asserted to reactivate the outputs. The CY7C0430BV and CY7C0430CV (64K x 18 device) supports burst contains for simple array partitioning. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst Page 2 of 37 CY7C0430BV CY7C0430CV counter is loaded with an external address when the port's Counter Load pin (CNTLD) is asserted LOW. When the port's Counter Increment pin (CNTINC) is asserted, the address counter will increment on each subsequent LOW-to- HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. The counter can address the entire switch array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. A counter-mask register is used to control the counter wrap. The counter and mask register operations are described in more details in the following sections. The counter or mask register values can be read back on the bidirectional address lines by activating MKRD or CNTRD, respectively. The new features included for the QuadPort DSE family include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, readback of mask register value on address lines, interrupt flags for message passing, BIST, JTAG for boundary scan, and asynchronous Master Reset. Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks[2] MRST UBP1 LBP1 R/WP1 OEP1 CE0P1 CE1P1 CLKP1 Reset Logic Port-1 Control Logic TMS TCK TDI CLKBIST JTAG Controller BIST TDO 18 I/O0P1- I/O17P1 CLKP1 A0P1-A15P1 MKLDP1 CNTLDP1 CNTINCP1 CNTRDP1 MKRDP1 CNTRSTP1 INTP1 CNTINTP1 16 Port 1 I/O Port 4 Logic Blocks[3] Port 1 Counter/ Mask Reg/ Address Decode Port 1 Port 4 64K x 18 QuadPort DSE Array Port 2 Port 3 Port 2 Logic Blocks[3] Port 3 Logic Blocks[3] Notes: 2. Port 1 Control Logic Block is detailed on page 4. 3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. Document #: 38-06027 Rev. *B Page 3 of 37 CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram (Address Readback is independent of CEs) R/WP1 W UBP1 CE0P1 CE1P1 LBP1 OEP1 I/O9P1-I/O17P1 I/O0P1-I/O8P1 9 9 Port-1 I/O Control Addr. Read Port 1 Readback Register MRST A0P1-A15P1 CNTRDP1 MKRDP1 MKLDP1 CNTINCP1 CNTLDP1 CNTRSTP1 CLKP1 MRST CNTINTP1 Priority Decision Logic 16 t1 Port 1 Mask Register Port 1 Address Decode Po rt Po r 4 Port 1 Counter/ Address Register LBP1 UBP1 R/WP1 CE0P1 CE1P1 OEP1 CLKP1 MRST 64K x 18 QuadPort DSE Array Port 1 Interrupt Logic INTP1 Document #: 38-06027 Rev. *B Page 4 of 37 Po r t3 Po 2 rt CY7C0430BV CY7C0430CV Pin Configuration 272-ball Grid Array (BGA) Top View 1 A B C D E F G H J K L M N P R T U V W Y LB P1 2 I/O17 P2 3 I/O15 P2 4 I/O13 P2 5 I/O11 P2 6 I/O9 P2 7 I/O16 P1 8 I/O14 P1 9 I/O12 P1 10 I/O10 P1 11 I/O10 P4 12 I/O12 P4 13 I/O14 P4 14 I/O16 P4 15 I/O9 P3 16 I/O11 P3 17 I/O13 P3 18 I/O15 P3 19 I/O17 P3 20 LB P4 VDD1 UB P1 I/O16 P2 I/O14 P2 I/O12 P2 I/O10 P2 I/O17 P1 I/O13 P1 I/O11 P1 TMS TDI I/O11 P4 I/O13 P4 I/O17 P4 I/O10 P3 I/O12 P3 I/O14 P3 I/O16 P3 UB P4 VDD1 A14 P1 A15 P1 CE1 P1 CE0 P1 R/W P1 I/O15 P1 VSS2 VSS2 I/O9 P1 TCK TDO I/O9 P4 VSS2 VSS2 I/O15 P4 R/W P4 CE0 P4 CE1 P4 A15 P4 A14 P4 VSS1 A12 P1 A13 P1 OE P1 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE P4 A13 P4 A12 P4 VSS1 A10 P1 A11 P1 MKRD P1 CNTRD P1 CNTRD P4 MKRD P4 A11 P4 A10 P4 A7 P1 A8 P1 A9 P1 CNTINT P1 CNTINT P4 A9 P4 A8 P4 A7 P4 VSS1 A5 P1 A6 P1 CNTINC P1 CNTINC P4 A6 P4 A5 P4 VSS1 A3 P1 A4 P1 MKLD P1 CNTLD P1 GND[4] GND[4] GND[4] GND[4] CNTLD P4 MKLD P4 A4 P4 A3 P4 VDD1 A1 P1 A2 P1 VDD VDD A2 P4 A1 P4 VDD1 A0 P1 INT P1 CNTRST P1 CLK P1 GND[4] GND[4] GND[4] GND[4] CLK P4 CNTRST P4 INT P4 A0 P4 A0 P2 INT P2 CNTRST P2 VSS GND[4] GND[4] GND[4] GND[4] VSS CNTRST P3 INT P3 A0 P3 VDD1 A1 P2 A2 P2 CLK P2 GND[4] GND[4] GND[4] GND[4] CLK P3 A2 P3 A1 P3 VDD1 A3 P2 A4 P2 MKLD P2 CNTLD P2 CNTLD P3 MKLD P3 A4 P3 A3 P3 VSS1 A5 P2 A6 P2 CNTINC P2 CNTINC P3 A6 P3 A5 P3 VSS1 A7 P2 A8 P2 A9 P2 CNTINT P2 CNTINT P3 A9 P3 A8 P3 A7 P3 A10 P2 A11 P2 MKRD P2 CNTRD P2 CNTRD P3 MKRD P3 A11 P3 A10 P3 VSS1 A12 P2 A13 P2 OE P2 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE P3 A13 P3 A12 P3 VSS1 A14 P2 A15 P2 CE1 P2 CE0 P2 R/W P2 I/O6 P2 VSS2 VSS2 I/O0 P2 NC NC I/O0 P3 VSS2 VSS2 I/O6 P3 R/W P3 CE0 P3 CE1 P3 A15 P3 A14 P3 VDD1 UB P2 I/O7 P1 I/O5 P1 I/O3 P1 I/O1 P1 I/O8 P2 I/O4 P2 I/O2 P2 MRST CLKBIST I/O2 P3 I/O4 P3 I/O8 P3 I/O1 P4 I/O3 P4 I/O5 P4 I/O7 P4 UB P3 VDD1 LB P2 I/O8 P1 I/O6 P1 I/O4 P1 I/O2 P1 I/O0 P1 1/O7 P2 I/O5 P2 I/O3 P2 I/O1 P2 I/O1 P3 I/O3 P3 I/O5 P3 I/O7 P3 I/O0 P4 I/O2 P4 I/O4 P4 I/O6 P4 I/O8 P4 LB P3 Note: 4. Central Leads are for thermal dissipation only. They are connected to device VSS. Document #: 38-06027 Rev. *B Page 5 of 37 CY7C0430BV CY7C0430CV Selection Guide CY7C0430CV -133 fMAX2 Max Access Time (Clock to Data) Max Operating Current ICC Max Standby Current for ISB1 (All ports TTL Level) Max Standby Current for ISB3 (All ports CMOS Level) 133[1] 4.2 750 200 15 CY7C0430CV -100 100 5.0 600 150 15 Unit MHz ns mA mA mA Pin Definitions Port 1 A0P1-A15P1 I/O0P1-I/O17P1 CLKP1 LBP1 Port 2 A0P2-A15P2 I/O0P2-I/O17P2 CLKP2 LBP2 Port 3 A0P3-A15P3 I/O0P3-I/O17P3 CLKP3 LBP3 Port 4 A0P4-A15P4 I/O0P4-I/O17P4 CLKP4 LBP4 Description Address Input/Output. Data Bus Input/Output. Clock Input. This input can be free running or strobed. Maximum clock input rate is fMAX. Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte. Chip Enable Input. To select any port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Output Enable Input. This signal must be asserted LOW to enable the I/O data lines during read operations. OE is asynchronous input. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Master Reset Input. This is one signal for All Ports. MRST is an asynchronous input. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. CNTRSTP2 CNTRSTP3 CNTRSTP4 Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is second to MRST in priority with respect to counter and mask register operations. Mask Register Load Input. Asserting this signal LOW loads the mask register with the external address available on the address lines. MKLD operation has higher priority over CNTLD operation. Counter Load Input. Asserting this signal LOW loads the burst counter with the external address present on the address pins. Counter Increment Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. UBP1 CE0P1,CE1P1 UBP2 CE0P2,CE1P2 UBP3 CE0P3,CE1P3 UBP4 CE0P4,CE1P4 OEP1 OEP2 OEP3 OEP4 R/WP1 R/WP2 R/WP3 R/WP4 MRST CNTRSTP1 MKLDP1 MKLDP2 MKLDP3 MKLDP4 CNTLDP1 CNTLDP2 CNTLDP3 CNTLDP4 CNTINCP1 CNTINCP2 CNTINCP3 CNTINCP4 Document #: 38-06027 Rev. *B Page 6 of 37 CY7C0430BV CY7C0430CV Pin Definitions (continued) Port 1 CNTRDP1 Port 2 CNTRDP2 Port 3 CNTRDP3 Port 4 CNTRDP4 Description Counter Readback Input. When asserted LOW, the internal address value of the counter will be read back on the address lines. During CNTRD operation, both CNTLD and CNTINC must be HIGH. Counter readback operation has higher priority over mask register readback operation. Counter readback operation is independent of port chip enables. If address readback operation occurs with chip enables active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os) will be three-stated. The readback timing will be valid after one no-operation cycle plus tCD2 from the rising edge of the next cycle. Mask Register Readback Input. When asserted LOW, the value of the mask register will be readback on address lines. During mask register readback operation, all counter and MKLD inputs must be HIGH (see Counter and Mask Register Operations truth table). Mask register readback operation is independent of port chip enables. If address readback operation occurs with chip enables active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os) will be three-stated. The readback will be valid after one no-operation cycle plus tCD2 from the rising edge of the next cycle. Counter Interrupt Flag Output. Flag is asserted LOW for one clock cycle when the counter wraps around to location zero. Interrupt Flag Output. Interrupt permits communications between all four ports. The upper four memory locations can be used for message passing. Example of operation: INTP4 is asserted LOW when another port writes to the mailbox location of Port 4. Flag is cleared when Port 4 reads the contents of its mailbox. The same operation is applicable to ports 1, 2, and 3. JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. JTAG Test Clock Input. This can be CLK of any port or an external clock connected to the JTAG TAP. JTAG Test Data Input. This is the only data input. TDI inputs will shift data serially in to the selected register. JTAG Test Data Output. This is the only data output. TDO transitions occur on the falling edge of TCK. TDO normally three-stated except when captured data is shifted out of the JTAG TAP. BIST Clock Input. Thermal Ground for Heat Dissipation. Ground Input. Power Input. Address Lines Ground Input. Address Lines Power Input. Data Lines Ground Input. Data Lines Power Input. MKRDP1 MKRDP2 MKRDP3 MKRDP4 CNTINTP1 CNTINTP2 CNTINTP3 CNTINTP4 INTP1 INTP2 INTP3 INTP4 TMS TCK TDI TDO CLKBIST GND VSS VDD VSS1 VDD1 VSS2 VDD2 Document #: 38-06027 Rev. *B Page 7 of 37 CY7C0430BV CY7C0430CV Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................-55C to + 125C Supply Voltage to Ground Potential .............. -0.5V to + 4.6V DC Voltage Applied to Outputs in High-Z State..........................-0.5V to VCC + 0.5V DC Input Voltage....................................-0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2200V Latch-up Current..................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 150 mV 3.3V 150 mV Electrical Characteristics Over the Operating Range Quadport DSE Family -133 Parameter VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Output HIGH Voltage (VCC = Min., IOH = -4.0 mA) Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled, CE = VIL, f = fmax Standby Current (four ports toggling at TTL Levels,0 active) CE1-4 VIH, f = fMAX Standby Current (four ports toggling at TTL Levels, 1 active) CE1 | CE2 | CE3 | CE4 < VIL, f = fMAX Standby Current (four ports CMOS Level, 0 active) CE1-4 VIH, f = 0 Standby Current (four ports CMOS Level, 1 active and toggling) CE1 | CE2 | CE3 | CE4 < VIL, f = fMAX -10 350 80 2.0 0.8 10 700 200 -10 300 60 Min. 2.4 0.4 2.0 0.8 10 550 150 Typ. Max. Min. 2.4 0.4 -100 Typ. Max. Unit V V V V A mA mA 150 300 125 250 mA 1.5 110 15 290 1.5 85 15 240 mA mA JTAG TAP Electrical Characteristics Over the Operating Range Parameter VOH1 VOL1 VIH VIL IX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND VI VDD Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V -100 Test Conditions IOH = -4.0 mA IOL = 4.0 mA 2.0 0.8 100 Min. 2.4 0.4 Max. Unit V V V V A Capacitance Parameter CIN (All Pins) COUT (All Pins) CIN (CLK Pins) COUT (CLK Pins) Description Input Capacitance Output Capacitance Input Capacitance Output Capacitance Max. 10 10 15 15 Unit pF pF pF pF Document #: 38-06027 Rev. *B Page 8 of 37 CY7C0430BV CY7C0430CV AC Test Load OUTPUT Z0 = 50 C [5] VTH = 1.5V R = 50 OUTPUT Z0 = 50 5 pF VTH = 1.5V R = 50 (a) Normal Load OUTPUT Z0 = 50 5 pF VTH = 3.3V 1.5V 50 TDO Z0 =50 C = 10 pF 3.0V GND GND 10% tR 90% R = 50 (b) Three-State Delay 90% 10% tF (c) TAP Load Note: 5. Test conditions: C = 10 pF. All Input Pulses Document #: 38-06027 Rev. *B Page 9 of 37 CY7C0430BV CY7C0430CV Switching Characteristics Over the Industrial Operating Range [6] CY7C0430BV and CY7C0430CV -133 Parameter fMAX2[7] tCYC2[7] tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSB tHB tSCLD tHCLD tSCINC tHCINC tSCRST tHCRST tSCRD tHCRD tSMLD tHMLD tSMRD tHMRD tOE tOLZ[8] tOHZ[8] tCD2 tCA2 tCM2 tDC tCKHZ[9] Maximum Frequency Clock Cycle Time Clock HIGH Time Clock LOW Time Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time Byte Set-up Time Byte Hold Time CNTLD Set-up Time CNTLD Hold Time CNTINC Set-up Time CNTINC Hold Time CNTRST Set-up Time CNTRST Hold Time CNTRD Set-up Time CNTRD Hold Time MKLD Set-up Time MKLD Hold Time MKRD Set-up Time MKRD Hold Time Output Enable to Data Valid OE to Low-Z OE to High-Z Clock to Data Valid Clock to Counter Address Readback Valid Clock to Mask Register Readback Valid Data Output Hold After Clock HIGH Clock HIGH to Output High-Z 1 1 4.8 1 1 6 4.2 4.7 4.7 1 1 6.8 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 2.3 0.7 6.5 1 1 7 5 5 5 7.5 3 3 2 2 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 3 0.7 8 Description Min. Max. 133 10 4 4 3 3 Min. -100 Max. 100 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 6. If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data remaining in the address is undefined. 7. fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns. 8. This parameter is guaranteed by design, but it is not production tested. 9. Valid for both address and data outputs. Document #: 38-06027 Rev. *B Page 10 of 37 CY7C0430BV CY7C0430CV Switching Characteristics Over the Industrial Operating Range (continued)[6] CY7C0430BV and CY7C0430CV -133 Parameter tCKLZ[9] tSINT tRINT tSCINT tRCINT tRS tRSR tROF tCCS[6] Description Clock HIGH to Output Low-Z Clock to INT Set Time Clock to INT Reset Time Clock to CNTINT Set Time Clock to CNTINT Reset Time Master Reset Pulse Width Master Reset Recovery Time Master Reset to Output Flags Reset Time Clock to Clock Set-up Time (time required after a write before you can read the same address location) 6.5 Min. 1 1 1 1 1 7.5 7.5 6.5 9 7.5 7.5 7.5 7.5 Max. Min. 1 1 1 1 1 10 10 8 10 10 10 10 -100 Max. Unit ns ns ns ns ns ns ns ns ns Master Reset Timing Port to Port Delays JTAG Timing and Switching Waveforms Quadport DSE Family -133/-100 Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX fBIST tBH tBL Description Maximum JTAG TAP Controller Frequency TCK Clock Cycle Time TCK Clock High Time TCK Clock Low Time TMS Set-up to TCK Clock Rise TMS Hold After TCK Clock Rise TDI Set-up to TCK Clock Rise TDI Hold after TCK Clock Rise TCK Clock Low to TDO Valid TCK Clock Low to TDO Invalid Maximum CLKBIST Frequency CLKBIST High Time CLKBIST Low Time 6 6 0 50 100 40 40 20 20 20 20 20 Min. Max. 10 Unit MHz ns ns ns ns ns ns ns ns ns MHz ns ns Document #: 38-06027 Rev. *B Page 11 of 37 CY7C0430BV CY7C0430CV tTH Test Clock TCK tTCYC tTMSS tTMSH tTL Test Mode Select TMS tTDIS Test Data-In TDI Test Data-Out TDO tTDIH tTDOX Switching Waveforms Master Reset[10] tCH2 CLK tRS tRSF tRSR INACTIVE tS ACTIVE tCYC2 tCL2 tTDOV MRST ALL ADDRESS/ DATA LINES ALL OTHER INPUTS TMS[11] CNTINT INT TDO Notes: 10. tS is the set-up time required for all input control signals. 11. To Reset the test port without resetting the device, TMS must be held low for five clock cycles. Document #: 38-06027 Rev. *B Page 12 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Read Cycle[12, 13, 14, 15, 16] tCH2 CLK tCYC2 tCL2 CE tSC LB tSB UB tHB tHC tSC tHC R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE tOE Notes: 12. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge. 13. CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH. 14. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 15. Addresses do not have to be accessed sequentially. Note 13 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference only. 16. CE is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH. An+2 tDC Qn+1 tOHZ An+3 Qn+2 tOLZ Document #: 38-06027 Rev. *B Page 13 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Bank Select Read[17, 18] tCH2 CLK tSA ADDRESS(B1) tSC CE(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 Q2 tCKLZ tCKHZ tCD2 Q4 tSC Q0 tDC A2 tHC tHC tCD2 Q1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A0 tHC tHA A1 A2 A3 A4 A5 tCYC2 tCL2 Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] tCH2 CLK tCYC2 tCL2 CE tSC tHC tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn tHW An+1 An+2 tHW An+2 tSD tHD An+3 An+4 tCKHZ Dn+2 tCD2 Qn+3 tCKLZ DATAOUT Read No Operation Write Read Notes: 17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one QuadPort DSE device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 18. LB = UB = OE = CNTLD = VIL; MRST = CNTRST= MKLD = VIH. 19. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 20. LB = UB = CNTLD = VIL; MRST = CNTRST = MKLD = VIH. 21. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only. 22. During "No Operation," data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06027 Rev. *B Page 14 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] tCH2 CLK tCYC2 tCL2 CE tSC tHC tSW tHW R/W tSW An tSA tHW An+1 tHA tCD2 An+2 tSD tHD Dn+2 Dn+3 tCD2 Qn tOHZ tCKLZ Qn+4 An+3 An+4 An+5 ADDRESS DATAIN DATAOUT OE Read Write Read Read with Address Counter Advance[23, 24] tCH2 CLK tSA ADDRESS tSCLD CNTLD tSCINC CNTINC tCD2 DATAOUT Qx-1 Read External Address Qx tDC Qn Read with Counter Qn+1 Counter Hold Qn+2 Read with Counter Qn+3 tHCINC An tHCLD tHA tCYC2 tCL2 Notes: 23. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH. 24. The "Internal Address" is equal to the "External Address" when CNTLD = VIL. Document #: 38-06027 Rev. *B Page 15 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Write with Address Counter Advance [24, 25] tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2 INTERNAL ADDRESS tSCLD CNTLD tHCLD An An+1 An+2 An+3 An+4 CNTINC tSCINC DATAIN tSD Dn tHD Write External Address tHCINC Dn+1 Write with Counter Dn+1 Write Counter Hold Dn+2 Dn+3 Dn+4 Write with Counter Note: 25. CE0 = LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH. Document #: 38-06027 Rev. *B Page 16 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Counter Reset [21, 26, 27] tCH2 CLK tSA ADDRESS INTERNAL ADDRESS R/W tSCLD CNTLD tHCLD AX tSW tHW A0 A1 An An tHA An+1 An+1 tCYC2 tCL2 CNTINC tSCRST CNTRST DATAIN DATAOUT Counter Reset Write Address 0 Read Address 0 tHCRST tSD D0 Q0 Read Address 1 Read Address n Q1 Qn tHD An+2 Notes: 26. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH. 27. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06027 Rev. *B Page 17 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Load and Read Address Counter[28] tCH2 CLK tSA A0-A15 tSCLD CNTLD CNTINC tSCINC CNTRD tHCINC An tHCLD tHA tCYC2 tCL2 Note 29 tCKLZ tCA2 Note 30 tCKHZ An+2[31] tSCRD tHCRD INTERNAL ADDRESS An tCD2 An+1 tDC Qn Read Data with Counter An+2 An+2 An+2 tCKHZ tCKLZ Qn+2 Read Internal Address DATAOUT Qx-1 Load External Address Qx Qn+1 Qn+2 Notes: 28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH. 29. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle. 30. Address in input mode. Host can drive address bus after tCKHZ. 31. This is the value of the address counter being read out on the address lines. Document #: 38-06027 Rev. *B Page 18 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Load and Read Mask Register [32] tCH2 CLK tSA A0-A15 tSMLD MKLD An tHMLD tHA tCYC2 tCL2 Note 29 tCKLZ tCA2 Note 30 tCKHZ An [33] tSMRD MKRD MASK INTERNAL VALUE Load Mask Register Value Notes: 32. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH. 33. This is the value of the Mask Register read out on the address lines. tHMRD An An An An Read Mask Register Value An Document #: 38-06027 Rev. *B Page 19 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Port 1 Write to Port 2 Read[34, 35, 36] tCH2 CLKP1 tSA PORT-1 ADDRESS tSW R/WP1 tCKHZ tSD Dn tCYC2 tCL2 tCH2 tSA An tHA tCCS tHD An tHW tHA tCYC2 tCL2 PORT-1 DATAIN tCKLZ CLKP2 PORT-2 ADDRESS R/WP2 tCD2 PORT-2 DATAOUT tDC Qn Notes: 34. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH. 35. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate data will be read out. 36. If tCCS< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of Port 2's clock. If tCCS > minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2's clock. Document #: 38-06027 Rev. *B Page 20 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Counter Interrupt [37, 38, 39] tCH2 CLK tCYC2 tCL2 EXTERNAL ADDRESS tSMLD MKLD 007Fh xx7Dh tHMLD tSCLD CNTLD tHCLD tSCINC CNTINC tHCINC COUNTER INTERNAL ADDRESS CNTINT An xx7Dh xx7Eh xx7Fh tSCINT xx00h xx00h tRCINT Mailbox Interrupt Timing[40, 41, 42, 43, 44] tCH2 CLKP1 tSA PORT-1 ADDRESS INTP2 tCYC2 tCL2 tHA An tSINT tRINT An+1 An+2 An+3 tCYC2 tCL2 FFFE tCH2 CLKP2 tSA PORT-2 ADDRESS Am tHA Am+1 FFFE Am+3 Am+4 Notes: 37. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH. 38. CNTINT is always driven. 39. CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The "x" is "Don't Care." 40. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH. 41. Address "FFFE" is the mailbox location for Port 2. 42. Port 1 is configured for Write operation, and Port 2 is configured for Read operation. 43. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox. 44. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock. Document #: 38-06027 Rev. *B Page 21 of 37 CY7C0430BV CY7C0430CV Table 1. Read/Write and Enable Operation (Any Port)[45, 46, 47] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs I/O0-I/O17 High-Z High-Z DIN DOUT High-Z Deselected Deselected Write Read Outputs Disabled Operation Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)[45, 48, 49] CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD X L X X X X X X Mode MasterReset Reset Load Load Operation Counter/Address Register Reset and Mask Register Set (resets entire chip as per reset state table) Counter/Address Register Reset Load of Address Lines into Mask Register Load of Address Lines into Counter/Address Register H H H H H H H L H H H H H H X L H H H H H X X L H H H H X X X L H H H X X X X L H H X X X X X L H Increment Counter Increment Readback Readback Counter on Address Lines Readback Readback Mask Register on Address Lines Hold Counter Hold Notes: 45. "X" = "Don't Care," "H" = VIH, "L" = VIL. 46. OE is an asynchronous input signal. 47. When CE changes state, deselection and read happen after one cycle of latency. 48. CE0 = OE = VIL; CE1 = R/W = VIH. 49. Counter operation and mask register operation are independent of Chip Enables. Document #: 38-06027 Rev. *B Page 22 of 37 CY7C0430BV CY7C0430CV Master Reset The QuadPort DSE device undergoes a complete reset by taking its Master Reset (MRST) input LOW. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). A Master Reset also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH, resets the BIST controller, and takes all registered control signals to a deselected read state.[50] A Master Reset must be performed on the QuadPort DSE device after power-up. the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is the mailbox for Port 3, and FFFC is the mailbox for Port 4. Table 3 shows that in order to set Port 1 INTP1 flag, a write by any other port to address FFFF will assert INTP1 LOW. A read of FFFF location by Port 1 will reset INTP1 HIGH. When one port writes to the other port's mailbox, the Interrupt flag (INT) of the port that the mailbox belongs to is asserted LOW. The Interrupt is reset when the owner (port) of the mailbox reads the contents of the mailbox. The interrupt flag is set in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port's mailbox without resetting the interrupt. If an application does not require message passing, INT pins should be treated as no-connect and should be left floating. When two ports or more write to the same mailbox at the same time INT will be asserted but the contents of the mailbox are not guaranteed to be valid. Interrupts The upper four memory locations may be used for message passing and permit communications between ports. Table 3 shows the interrupt operation for all ports. For the 1-Mb QuadPort DSE device, the highest memory location FFFF is Table 3. Interrupt Operation Example Port 1 Function Set Port 1 INTP1 Flag Reset Port 1 INTP1 Flag Set Port 2 INTP2 Flag Reset Port 2 INTP2 Flag Set Port 3 INTP3 Flag Reset Port 3 INTP3 Flag Set Port 4 INTP4 Flag Reset Port 4 INTP4 Flag A0P1-15P1 X FFFF FFFE X FFFD X FFFC X INTP1 L H X X X X X X Port 2 A0P2-15P2 FFFF X X FFFE FFFD X FFFC X INTP2 X X L H X X X X Port 3 A0P3-15P3 FFFF X FFFE X X FFFD FFFC X INTP3 X X X X L H X X Port 4 A0P4-15P4 FFFF X FFFE X FFFD X X FFFC INTP4 X X X X X X L H Note: 50. During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI = CNTINCI = VIH; CE1I = VIL. The "I" suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals. Document #: 38-06027 Rev. *B Page 23 of 37 CY7C0430BV CY7C0430CV Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. A port's burst counter is loaded with the port's Counter Load pin (CNTLD). When the port's Counter Increment (CNTINC) is asserted, the address counter will increment on each LOW to HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. Depending on the mask register state, the counter can address the entire memory array and will loop back to start. Counter Reset (CNTRST) is used to reset the Burst Counter (the Mask Register value is unaffected). When using the counter in readback mode, the internal address value of the counter will be read back on the address lines when Counter Readback Signal (CNTRD) is asserted. Figure 1 provides a block diagram of the readback operation. Table 2 lists control signals required for counter operations. The signals are listed based on their priority. For example, Master Reset takes precedence over Counter Reset, and Counter Load has lower priority than Mask Register Load (described below). All counter operations are independent of Chip Enables (CE0 and CE1). When the address readback operation is performed the data I/Os are three-stated (if CEs are active) and one-clock cycle (no-operation cycle) latency is experienced. The address will be read at time tCA2 from the rising edge of the clock following the no-operation cycle. The read back address can be either of the burst counter or the mask register based on the levels of Counter Read signal (CNTRD) and Mask Register Read signal (MKRD). Both signals are synchronized to the port's clock as shown in Table 2. Counter read has a higher priority than mask read. CNTRD MKRD Readback Register Addr. Readback MKLD = 1 Bidirectional Address Lines Mask Register Memory Array CNTINC = 1 CNTLD = 1 CNTRST = 1 CLK Counter/ Address Register Figure 1. Counter and Mask Register Read Back on Address Lines Document #: 38-06027 Rev. *B Page 24 of 37 CY7C0430BV CY7C0430CV Counter-Mask Register Example: Load Counter-Mask Register = 3F CNTINT H 00 215 214 Blocked Address Load Address Counter = 8 H XX 215 214 Max Address Register Max + 1 Address Register H XX 215 214 L XX 215 214 The burst counter has a mask register that controls when and where the counter wraps. An interrupt flag (CNTINT) is asserted for one clock cycle when the unmasked portion of the counter address wraps around from all ones (CNTINC must be asserted) to all zeros. The example in Figure 2 shows the counter mask register loaded with a mask value of 003F unmasking the first 6 bits with bit "0" as the LSB and bit "15" as the MSB. The maximum value the mask register can be loaded with is FFFF. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of XXX8. The "blocked" addresses (in this case, the 6th address through the 15th address) are loaded with an address but do not increment once loaded. The counter address will start at address XXX8. With CNTINC asserted LOW, the counter will increment its internal address value till it reaches the mask register value of 3F and wraps around the memory block to location XXX0. Therefore, the counter uses the mask-register to define wrap-around point. The mask register of every port is loaded when MKLD (mask register load) for that port is LOW. When MKRD is LOW, the value of the mask register can be read out on address lines in a manner similar to counter read back operation (see Table 2 for required conditions). When the burst counter is loaded with an address higher than the mask register value, the higher addresses will form the masked portion of the counter address and are called blocked addresses. The blocked addresses will not be changed or affected by the counter increment operation. The only exception is mask register bit 0. It can be masked to allow the address counter to increment by two. If the mask register bit 0 is loaded with a logic value of "0," then address counter bit 0 is masked and can not be changed during counter increment operation. If the loaded value for address counter bit 0 is "0," Note: 51. The "X" in this diagram represents the counter upper-bits. 0's 011 1 1 1 1 Mask Register bit-0 0 Address Counter bit-0 26 25 24 23 22 21 20 Counter Address X00 1 0 0 X's 26 25 24 23 22 21 20 X's X11 1 11 1 26 25 24 23 22 21 20 X's X0 0 0 00 0 26 25 24 23 22 21 20 the counter will increment by two and the address values are even. If the loaded value for address counter bit 0 is "1," the counter will increment by two and the address values are odd. This operations allows the user to achieve a 36-bit interface using any two ports, where the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 36-bit word in even memory locations, and the other half in odd memory locations. CNTINT will be asserted when the unmasked portion of the counter wraps to all zeros. Loading mask register bit 0 with "1" allows the counter to increment the address value sequentially. Table 2 groups the operations of the mask register with the operations of the address counter. Address counter and mask register signals are all synchronized to the port's clock CLK. Master reset (MRST) is the only asynchronous signal listed on Table 2. Signals are listed based on their priority going from left column to right column with MRST being the highest. A LOW on MRST will reset both counter register to all zeros and mask register to all ones. On the other hand, a LOW on CNTRST will only clear the address counter register to zeros and the mask register will remain intact. There are four operations for the counter and mask register: 1. Load operation: When CNTLD or MKLD is LOW, the address counter or the mask register is loaded with the address value presented at the address lines. This value ranges from 0 to FFFF (64K). The mask register load operation has a higher priority over the address counter load operation. 2. Increment: Once the address counter is loaded with an external address, the counter can internally increment the address value by asserting CNTINC LOW. The counter can Figure 2. Programmable Counter-Mask Register Operation[51] Document #: 38-06027 Rev. *B Page 25 of 37 CY7C0430BV CY7C0430CV address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to load operation. 3. Readback: the internal value of either the burst counter or the mask register can be read out on the address lines when CNTRD or MKRD is LOW. Counter readback has higher priority over mask register readback. A no-operation delay cycle is experienced when readback operation is performed. The address will be valid after tCA2 (for counter readback) or tCM2 (for mask readback) from the following port's clock rising edge. Address readback operation is independent of the port's chip enables (CE0 and CE1). If address readback occurs while the port is enabled (chip enables active), the data lines (I/Os) will be three-stated. 4. Hold operation: In order to hold the value of the address counter at certain address, all signals in Table 2 have to be HIGH. This operation has the least priority. This operation is useful in many applications where wait states are needed or when address is available few cycles ahead of data. The counter and mask register operations are totally independent of port chip enables. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram (FSM)). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the QuadPort DSE device and may be performed while the device is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the QuadPort DSE device test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Four-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the following JTAG/BIST Controller diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain devices. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the QuadPort DSE device with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the QuadPort DSE device. The boundary scan register is loaded with the contents of the QuadPort DSE device Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) The CY7C0430BV and CY7C0430CV incorporate a serial boundary scan test access port (TAP). This port is fully compatible with IEEE Standard 1149.1-2001[52]. The TAP operates using JEDEC standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Memory BIST circuitry will also be controlled through the TAP interface. All MBIST instructions are compliant to the JTAG standard. An external clock (CLKBIST) is provided to allow the user to run BIST at speeds up to 50 MHz. CLKBIST is multiplexed internally with the ports clocks during BIST operation. Disabling the JTAG Feature It is possible to operate the QuadPort DSE device without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. CLKBIST must be tied LOW to disable the MBIST. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP)-Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Note: 52. Master Reset will reset the JTAG controller. Document #: 38-06027 Rev. *B Page 26 of 37 CY7C0430BV CY7C0430CV The EXTEST, and SAMPLE/PRELOAD instructions can be used to capture the contents of the Input and Output ring. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the QuadPort DSE device and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Sixteen different instructions are possible with the 4-bit instruction register. All combinations are listed in Table 6, Instruction Codes. Seven of these instructions (codes) are listed as RESERVED and should not be used. The other nine instructions are described in detail below. The TAP controller used in this QuadPort DSE device is fully compatible[52] with the 1149.1 convention. The TAP controller can be used to load address, data or control signals into the QuadPort DSE device and can preload the Input or output buffers. The QuadPort DSE device implements all of the 1149.1 instructions except INTEST. Table 6 lists all instructions. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST allows circuitry external to the QuadPort DSE device package to be tested. Boundary-scan register cells at output pins are used to apply test stimuli, while those at input pins capture test results. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places the identification register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. High-Z The High-Z instruction causes the bypass register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all QuadPort DSE device outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the QuadPort DSE device clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the QuadPort DSE device signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. If the TAP controller goes into the Update-DR state, the sampled data will be updated. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. CLAMP The optional CLAMP instruction allows the state of the signals driven from QuadPort DSE device pins to be determined from the boundary-scan register while the BYPASS register is selected as the serial path between TDI and TDO. CLAMP controls boundary cells to 1 or 0. CYBIST CYBIST instruction provides the user with a means of running a user-accessible self-test function within the QuadPort DSE device as a result of a single instruction. This permits all components on a board that offer the CYBIST instruction to execute their self-tests concurrently, providing a quick check for the board. The QuadPort DSE device MBIST provides two modes of operation once the TAP controller is loaded with the CYBIST instruction: Non-Debug Mode (Go-NoGo) The non-debug mode is a go-nogo test used simply to run BIST and obtain pass-fail information after the test is run. In addition to that, the total number of failures encountered can be obtained. This information is used to aid the debug mode (explained next) of operation. The pass-fail information and failure count is scanned out using the JTAG interface. An MBIST Result Register (MRR) will be used to store the pass-fail results. The MRR is a 25-bit register that will be connected between TDI and TDO during the internal scan (INT_SCAN) operation. The MRR will contain the total number of fail read cycles of the entire MBIST sequence. MRR[0] (bit 0) is the Pass/Fail bit. A "1" indicates some type of failure occurred, and a "0" indicates entire memory pass. In order to run BIST in non-debug mode, the two-bit MBIST Control Register (MCR) is loaded with the default value "00", and the TAP controller's finite state machine (FSM), which is synchronous to TCK, transitions to Run Test/Idle state. The entire MBIST test will be performed with a deterministic Document #: 38-06027 Rev. *B Page 27 of 37 CY7C0430BV CY7C0430CV number of TCK cycles depending on the TCK and CLKBIST frequency. t CYC [ CLKBIST ] t CYC = -------------------------------------------- x m + SPC t CYC [ TCK ] tCYC is total number of TCK cycles required to run MBIST. SPC is the Synchronization Padding Cycles (4-6 cycles). m is a constant represents the number of read and write operations required to run MBIST algorithms (31195136). Once the entire MBIST sequence is completed, supplying extra TCK or CLKBIST cycles will have no effect on the MBIST controller state or the pass-fail status. Debug Mode With the CYBIST instruction loaded and the MCR loaded with the value of "01," and the FSM transitions to RUN_TEST/IDLE state, the MBIST goes into CYBIST-debug mode. The debug mode will be used to provide complete failure analysis information at the board level. It is recommended that the user runs the non-debug mode first and then the debug mode in order to save test time and to set an upper bound on the number of scan outs that will be needed. The failure data will be scanned out automatically once a failure occurs using the JTAG TAP interface. The failure data will be represented by a 100-bit packet given below. The 100-bit Memory Debug Register (MDR) will be connected between TDI and TDO, and will be shifted out on TDO, which is synchronized to TCK. Figure 3 is a representation of the 100-bit MDR packet. The packet follows a two-bit header that has a logic "1" value, and represents two TCK cycles. MDR[97:26] represent the BIST comparator values of all four ports (each port has 18 data lines). A value of "1" indicates a bit failure. The scanned out data is from LSB to MSB. MDR[25:10] represent the failing address (MSB to LSB). The state of the BIST controller is scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A "0" in bit 2 means test not complete. The user has to monitor this bit at every packet to determine if more failure packets need to be scanned out at the end of the BIST operations. If the value is "0" then BIST must be repeated to capture the next failing packet. If it is "1," it means that the last failing packets have been scanned out. A trailer similar to the header represents the end of a packet. MCR_SCAN This instruction will connect the Memory BIST Control Register (MCR) between TDI and TDO. The default value (upon master reset) is "00." Shift_DR state will allow modifying the MCR to extend the MBIST functionality. MBIST Control States Thirty-five states are listed in Table 7. Four data algorithms are used in debug mode: moving inversion (MIA), march_2 (M2A), checkerboard (CBA), and unique address algorithm (UAA). Only Port 1 can write MIA, M2A, and CBA data to the memory. All four ports can read any algorithm data from the QuadPort DSE device memory. Ports 2, 3, and 4 will only write UAA data. Boundary Scan Cells (BSC) Table 9 lists all QuadPort DSE family I/Os with their associated BSC. Note that the cells have even numbers. Every I/O has two boundary scan cells. Bidirectional signals (address lines, datalines) require two cells so that one (the odd cell) is used to control a three-state buffer. Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout. 99 1 97 98 1 62 P3_IO(17-9) P3_IO(8-0) 10 4 P2_IO(17-9) P2_IO(8-0) P1_IO(17-9) 26 P1_IO(8-0) P4_IO(17-9) 61 P4_IO(8-0) 25 A(15-0) 9 MBIST_State 3 P/F 2 TD 1 1 1 0 Figure 3. MBIST Debug Register Packet Document #: 38-06027 Rev. *B Page 28 of 37 CY7C0430BV CY7C0430CV TAP Controller State Diagram (FSM)[53] 1 TEST-LOGIC RESET 0 0 RUN_TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 Note: 53. The "0"/"1" next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06027 Rev. *B Page 29 of 37 CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram 0 Bypass Register (BYR) 1 0 MBIST Control Register (MCR) 32 1 0 Instruction Register (IR) 24 23 TDI 0 Selection Circuitry TDO MBIST Result Register (MRR) 31 30 29 0 Identification Register (IDR) 99 0 MBIST Debug Register (MDR) 391 0 Boundary Scan Register (BSR) (MUX) BIST CONTROLLER CLKBIST TAP CONTROLLER TCK TMS MRST MEMORY CELL Table 4. Identification Register Definitions Instruction Field Revision Number (31:28) Cypress Device ID (27:12) Cypress JEDEC ID (11:1) ID Register Presence (0) 1h C000h 34h 1 Value Description Reserved for version number Defines Cypress part number Allows unique identification of QuadPort DSE device vendor Indicate the presence of an ID register Document #: 38-06027 Rev. *B Page 30 of 37 CY7C0430BV CY7C0430CV Table 5. Scan Registers Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) MBIST Control (MCR) MBIST Result (MRR) MBIST Debug (MDR) Boundary Scan (BSR) Table 6. Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD CYBIST INT_SCAN MCR_SCAN RESERVED 0000 1111 0111 0110 0101 0001 1000 0010 0011 All other codes Code Description Captures the Input/Output ring contents. Places the boundary scan register (BSR) between the TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the BYR between TDI and TDO. Forces all QuadPort DSE device output drivers to a High-Z state. Controls boundary to 1/0. Uses BYR. Captures the Input/Output ring contents. Places the boundary scan register (BSR) between TDI and TDO. Invokes MBIST. Places the MBIST Debug register (MDR) between TDI and TDO. Scans out pass-fail information. Places MBIST Result Register (MRR) between TDI and TDO. Presets CYBIST mode. Places MBIST Control Register (MCR) between TDI and TDO. Seven combinations are reserved. Do not use other than the above. 4 1 32 2 25 100 392 Bit Size Table 7. MBIST Control States States Code 000001 000011 State Name movi_zeros movi_1_upcnt Description Port 1 write all zeros to the QuadPort DSE device memory using Moving Inversion Algorithm (MIA). Up count from 0 to 64K (depth of QuadPort DSE device). All ports read 0s, then Port 1 writes 1s to all memory locations using MIA, then all ports read 1s. MIA read0_write1_read1 (MIA_r0w1r1). Up count from 0 to 64K. All ports read 1s, then Port 1 writes 0s, then all ports read 0s (MIA_r1w0r0). Down count from 64K to 0. MIA_r0w1r1. Down count MIA_r1w0r0. Read all 0s. Port 1 write all zeros to memory using March2 Algorithm (M2A). Up count M2A_r0w1r1. Up count M2A_r1w0r0. Down count M2A_r0w1r1. Down count M2A_r1w0r0. Read all 0s. Port 1 writes topological checkerboard data to memory. Page 31 of 37 000010 000110 000111 000101 000100 001100 001101 001111 001110 001010 001011 movi_0_upcnt movi_1_downcnt movi_0_downcnt movi_read mar2_zeros mar2_1_upcnt mar2_0_upcnt mar2_1_downcnt mar2_0_downcnt mar2_read chkr_w Document #: 38-06027 Rev. *B CY7C0430BV CY7C0430CV Table 7. MBIST Control States (continued) States Code 001001 001000 011000 011001 011011 011010 011110 011111 011101 011001 011011 011010 011110 011111 011101 011001 011011 011010 011110 011111 011101 110010 State Name chkr_r n_chkr_w n_chkr_r uaddr_zeros2 uaddr_write2 uaddr_read2 uaddr_ones2 n_uaddr_write2 n_uaddr_read2 uaddr_zeros3 uaddr_write3 uaddr_read3 uaddr_ones3 n_uaddr_write3 n_uaddr_read3 uaddr_zeros4 uaddr_write4 uaddr_read4 uaddr_ones4 n_uaddr_write4 n_uaddr_read4 complete Description All ports read topological checkerboard data. Port 1 write inverse topological checkerboard data. All ports read inverse topological checkerboard data. Port 2 write all zeros to memory using Unique Address Algorithm (UAA). Port 2 writes every address value into its memory location (UAA). All ports read UAA data. Port 2 writes all ones to memory. Port 2 writes inverse address value into memory. All ports read inverse UAA data. Port 3 write all zeros to memory using Unique Address Algorithm (UAA). Port 3 writes every address value into its memory location (UAA). All ports read UAA data. Port 3 writes all ones to memory. Port 3 writes inverse address value into memory. All ports read inverse UAA data. Port 4 write all zeros to memory using Unique Address Algorithm (UAA). Port 4 writes every address value into its memory location (UAA). All ports read UAA data. Port 4 writes all ones to memory. Port 4 writes inverse address value into memory. All ports read inverse UAA data. Test complete. Table 8. MBIST Control Register (MCR) MCR[1:0] 00 01 10 11 Mode Non-Debug Debug Reserved Reserved Document #: 38-06027 Rev. *B Page 32 of 37 CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order Cell # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 Signal Name A0_P4 A1_P4 A2_P4 A3_P4 A4_P4 A5_P4 A6_P4 A7_P4 A8_P4 A9_P4 A10_P4 A11_P4 A12_P4 A13_P4 A14_P4 A15_P4 CNTINT_P4 CNTRST_P4 MKLD_P4 CNTLD_P4 CNTINC_P4 CNTRD_P4 MKRD_P4 LB_P4 UB_P4 OE_P4 R/W_P4 CE1_P4 CE0_P4 INT_P4 CLK_P4 A0_P3 A1_P3 A2_P3 A3_P3 A4_P3 A5_P3 A6_P3 A7_P3 A8_P3 A9_P3 K20 J19 J18 H20 H19 G19 G18 F20 F19 F18 E20 E19 D19 D18 C20 C19 F17 K18 H18 H17 G17 E17 E18 A20 B19 D17 C16 C18 C17 K19 K17 L20 M19 M18 N20 N19 P19 P18 R20 R19 R18 Bump (Ball) ID Table 9. Boundary Scan Order (continued) Cell # 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 Signal Name A10_P3 A11_P3 A12_P3 A13_P3 A14_P3 A15_P3 CNTINT_P3 CNTRST_P3 MKLD_P3 CNTLD_P3 CNTINC_P3 CNTRD_P3 MKRD_P3 LB_P3 UB_P3 OE_P3 R/W_P3 CE1_P3 CE0_P3 INT_P3 CLK_P3 IO0_P4 IO1_P4 IO2_P4 IO3_P4 IO4_P4 IO5_P4 IO6_P4 IO7_P4 IO8_P4 IO0_P3 IO1_P3 IO2_P3 IO3_P3 IO4_P3 IO5_P3 IO6_P3 IO7_P3 IO8_P3 IO0_P1 IO1_P1 T20 T19 U19 U18 V20 V19 R17 L18 N18 N17 P17 T17 T18 Y20 W19 U17 V16 V18 V17 L19 M17 Y15 W15 Y16 W16 Y17 W17 Y18 W18 Y19 V12 Y11 W12 Y12 W13 Y13 V15 Y14 W14 Y6 W6 Bump (Ball) ID Document #: 38-06027 Rev. *B Page 33 of 37 CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Cell # 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 Signal Name IO2_P1 IO3_P1 IO4_P1 IO5_P1 IO6_P1 IO7_P1 IO8_P1 IO0_P2 IO1_P2 IO2_P2 IO3_P2 IO4_P2 IO5_P2 IO6_P2 IO7_P2 IO8_P2 A0_P2 A1_P2 A2_P2 A3_P2 A4_P2 A5_P2 A6_P2 A7_P2 A8_P2 A9_P2 A10_P2 A11_P2 A12_P2 A13_P2 A14_P2 A15_P2 CNTINT_P2 CNTRST_P2 MKLD_P2 CNTLD_P2 CNTINC_P2 CNTRD_P2 MKRD_P2 LB_P2 UB_P2 Y5 W5 Y4 W4 Y3 W3 Y2 V9 Y10 W9 Y9 W8 Y8 V6 Y7 W7 L1 M2 M3 N1 N2 P2 P3 R1 R2 R3 T1 T2 U2 U3 V1 V2 R4 L3 N3 N4 P4 T4 T3 Y1 W2 Bump (Ball) ID Table 9. Boundary Scan Order (continued) Cell # 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320 322 324 326 328 Signal Name OE_P2 R/W_P2 CE1_P2 CE0_P2 INT_P2 CLK_P2 A0_P1 A1_P1 A2_P1 A3_P1 A4_P1 A5_P1 A6_P1 A7_P1 A8_P1 A9_P1 A10_P1 A11_P1 A12_P1 A13_P1 A14_P1 A15_P1 CNTINT_P1 CNTRST_P1 MKLD_P1 CNTLD_P1 CNTINC_P1 CNTRD_P1 MKRD_P1 LB_P1 UB_P1 OE_P1 R/W_P1 CE1_P1 CE0_P1 INT_P1 CLK_P1 IO9_P2 IO10_P2 IO11_P2 IO12_P2 U4 V5 V3 V4 L2 M4 K1 J2 J3 H1 H2 G2 G3 F1 F2 F3 E1 E2 D2 D3 C1 C2 F4 K3 H3 H4 G4 E4 E3 A1 B2 D4 C5 C3 C4 K2 K4 A6 B6 A5 B5 Bump (Ball) ID Document #: 38-06027 Rev. *B Page 34 of 37 CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Cell # 330 332 334 336 338 340 342 344 346 348 350 352 354 356 358 360 362 364 366 368 370 372 374 376 378 380 382 384 386 388 390 392 Signal Name IO13_P2 IO14_P2 IO15_P2 IO16_P2 IO17_P2 IO9_P1 IO10_P1 IO11_P1 IO12_P1 IO13_P1 IO14_P1 IO15_P1 IO16_P1 IO17_P1 IO9_P3 IO10_P3 IO11_P3 IO12_P3 IO13_P3 IO14_P3 IO15_P3 IO16_P3 IO17_P3 IO9_P4 IO10_P4 IO11_P4 IO12_P4 IO13_P4 IO14_P4 IO15_P4 IO16_P4 IO17_P4 A4 B4 A3 B3 A2 C9 A10 B9 A9 B8 A8 C6 A7 B7 A15 B15 A16 B16 A17 B17 A18 B18 A19 C12 A11 B12 A12 B13 A13 C15 A14 B14 Bump (Ball) ID Ordering Information 10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K x 18) Speed (MHz) 133 100 Ordering Code CY7C0430BV-133BGI CY7C0430CV-133BGI CY7C0430BV-100BGC CY7C0430BV-100BGI Package Name BG272 BG272 BG272 BG272 Package Type 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) 272-ball Grid Array (BGA) Operating Range Industrial Industrial Commercial Industrial Document #: 38-06027 Rev. *B Page 35 of 37 CY7C0430BV CY7C0430CV Package Diagram 272-Lead PBGA (27 x 27 x 2.33 mm) BG272 51-85130-*A QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06027 Rev. *B Page 36 of 37 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0430BV CY7C0430CV Document History Page Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38-06027 REV. ** *A ECN NO. 109906 115042 Issue Date 09/10/01 05/23/02 Orig. of Change SZV FSG Description of Change Change from Spec number: 38-01052 to 38-06027 Remove Preliminary, TM from DSE Change RUNBIST to CYBIST Updated ISB values Added notes 7 and 9 Increased commercial prime bin to 135 MHz Part numbers updated to reflect the recent die revisions Removed 1/2M and 1/4M parts Changed title of data sheet *B 464083 SEE ECN YDT Document #: 38-06027 Rev. *B Page 37 of 37 |
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